1. Field of the Invention
The invention relates to phase-locked loop (PLL) circuits. More particularly, the invention relates to sampling phase detectors in all digital phase-locked loops.
2. Description of the Related Art
A phase-locked loop (PLL) is a circuit that generates a periodic output signal, or clock, that has a constant phase relationship with a periodic input signal. PLLs are closed loop frequency control systems whose operation depends on the detection of the phase difference between the input and output signals of the circuit, and are used in many types of measurement, microprocessor and communications applications.
Typically, a conventional PLL includes a phase/frequency detector (PFD), a charge pump, a loop filter, a voltage-controlled oscillator (VCO) to generate the PLL output clock, and a frequency divider. The PFD measures the difference in phase between an input clock and a feedback clock, which may be the PLL output clock itself, or a clock generated by passing the PLL output clock through the frequency divider, and generates an error signal that is proportional to the measured phase difference. The charge pump generates an amount of charge that is proportional to the error signal and inputs the charge to the loop filter. The loop filter outputs a VCO control voltage that is supplied to the VCO. The frequency of the PLL output clock generated by the VCO is controlled by the loop filter (VCO control) voltage supplied to the VCO.
Loop filters in conventional PLLs typically are analog loop filters that use passive components, such as capacitors and resistors. However, such components in these analog loop filters require a relatively large amount of chip area on an integrated circuit containing the PLL. The use of a digital loop filter and a completely digital PLL greatly reduces the chip area needed for the PLL.
The article “A Digitally Controlled PLL for SoC Applications,” IEEE Journal of Solid-State Circuits, Vol. 39, No. 5, May 2004, describes the design and fabrication of a fully integrated digitally controlled phase-locked loop (PLL) used as a clock multiplying circuit. The phase detector in this PLL is based on a time to digital converter, which is realized through the use of several counters. Although the digitally controlled PLL described in the article occupies an area of only approximately 0.07 mm2, its design is relatively complex compared to many conventional digital PLL designs.
Accordingly, it would be desirable to have available an all digital PLL that occupies less chip area than conventional PLLs that include analog components, and whose design is less complex than conventional digital PLLs.